HIGH VOLTAGE TOLERANT ELECTROSTATIC DISCHARGE (ESD) BUS CLAMP

摘要

A circuit for electrostatic discharge (ESD) protection of dual-voltage integrated circuit devices utilizes two cascoded P-channel field effect transistors (PFETs) and two timing networks to protect the integrated circuit devices from damage by ESD transients which may appear on either one of the two voltage supplies for the dual-voltage integrated circuit devices.