发明名称 Method and apparatus for improving resist pattern developing
摘要 An apparatus and method for developing a selectively exposed resist pattern, on an integrated circuit wafer, which avoids damage to the resist pattern and allows greater freedom in the choice of resists. Developer is placed on a selectively exposed layer of resist for a first time. The layer of resist and developer are then immersed in a cleaning liquid time for a second time to stop the developing action and remove the developer. As an option, ultrasonic power can be delivered to the wafer or the cleaning liquid while the layer of resist is immersed in the cleaning liquid. The cleaning liquid is then removed from the layer of resist, now a resist pattern, and the wafer and resist pattern is placed in a vacuum for drying. As another option, heat can be applied to the wafer and resist pattern while they are in the vacuum. The wafer and resist pattern are then removed from the vacuum for further processing.
申请公布号 US2002144707(A1) 申请公布日期 2002.10.10
申请号 US20020061661 申请日期 2002.02.04
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY 发明人 CHIU WEI-KAY
分类号 B41J2/145;G03F7/30;(IPC1-7):C23F1/00;C25F3/30 主分类号 B41J2/145
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