发明名称 Semiconductor package with central circuit pattern
摘要 A printed wired board is provided, in which an area for extracting lines for plating of the printed wired board is made small and at the same time the number of the extracting lines for plating within a packaging area is made small, resulting in an improvement of wiring efficiency. The circuit pattern formed on an insulating film has a window portion and is not formed toward the periphery of the insulating film, and a bonding pad is electroplated, where the bonding pads are to be connected with a center-pad of a semiconductor by a bonding wire through the window portion. Accordingly, even when the shrinkage of semiconductor packages or narrow ball pitch is forwarded, the degree of freedom of drawing of circuit pattern in the printed wired board can be made large.
申请公布号 US6462283(B1) 申请公布日期 2002.10.08
申请号 US19990390024 申请日期 1999.09.03
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 HIRAI SUMIE;OHMORI JUN
分类号 H01L23/12;H01L21/60;H01L23/13;H01L23/498;H05K1/00;H05K3/00;H05K3/24;(IPC1-7):H05K1/16;H01R9/09 主分类号 H01L23/12
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