| 摘要 |
An ESD protection circuit layout. The ESD protection circuit layout has a first ESD protection device, a second ESD protection device, a first CDM ESD protection device, a second CDM ESD protection device, a first charge flow prevention device, a PMOS transistor, an input resistor, an NMOS transistor, a second charge flow prevention device and a substrate resistor. Charges within an integrated circuit device are discharged through a discharging loop comprising of the first CDM ESD protection device and the second CDM ESD protection device. Ultimately, the integrated circuit device is protected against CDM ESD and electrical latch-up within the integrated circuit is also minimized.
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