| 摘要 |
Integrated circuits incorporating latching sense amplifier circuits usually provide substantial latch timing margins. Excess latch timing margins may be reduced by using a latch timing circuit for controlling the timing of a latch enable signal which is both programmable and electrically configurable. Using the configurable capability, an integrated circuit may be tested while varying the latch enable timing to determine the most aggressive timing for which that particular integrated circuit functions without error. The latch timing circuit is also programmable so that this timing, or another timing, such as a somewhat less aggressive timing, may be programmed to thereafter be the timing normally generated by the latch timing circuit. For certain embodiments the latch timing circuit, after programming its timing, may again be temporarily configured to a more or less aggressive timing relative to the programmed timing, so that adequate operating margins may be ensured. Each particular integrated circuit may be tested to more optimally set the latch timing required by the individual integrated circuit.
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