发明名称 METHOD AND DEVICE FOR POWER CONSUMPTION EVALUATION
摘要 PROBLEM TO BE SOLVED: To provide a method to greatly shorten the time for simulation required for the number of times of toggle for output of each logic gate, in a circuit where power consumption is to be measured. SOLUTION: In the toggle detecting circuit, one-bit registers 101 and 102 are provided and each signal for times t-1 and t-2 is retained for input 100 at a time 't'. '1' is outputted by a detector 103 only for variations of from 0 to 1 and from 1 to 0 at the time 't'. Signals obtained by a detector 102 is added by an accumulator 104. The number of toggles are retained by a register 105 for a number of bits, and a toggle detection circuit 106 and a power consumption measuring circuit are realized to a programmable array, test vector for simulation is inputted and the toggle number of times is obtained by referring the result of the resistor 105, after the simulation is finished.
申请公布号 JP2002288257(A) 申请公布日期 2002.10.04
申请号 JP20010084451 申请日期 2001.03.23
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SUGISAWA YASUSHI
分类号 G01R31/28;G06F17/50;(IPC1-7):G06F17/50 主分类号 G01R31/28
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