| 摘要 |
<p>An encoder (4) comprises flip-flop circuits (4a, 4b) which latch two-system signals having B/2 transmission speed at a B/2 frequency and output them, an adder (4f) which adds the respective output signals of the flip-flop circuits (4a, 4b) and outputs the sum, and a delayer (4e) which delays the output signal from the flip-flop circuit (4b) by 1/B hr behind the output signal from the flip-flop circuit (4a) on the input timing of the adder (4f).</p> |
