| 发明名称 |
Timing recovery loop latency reduction via loop filter pre-calculation |
| 摘要 |
A circuit for use in a phase locked loop includes pre-computation blocks for phase error detector and loop filter functions, a selection block (or multiplexer) of these pre-computed results based on detected (or reference signal) signal, and on ambiguity zone detector deriving the pre-computation blocks.
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| 申请公布号 |
US2002141089(A1) |
申请公布日期 |
2002.10.03 |
| 申请号 |
US20010991602 |
申请日期 |
2001.11.21 |
| 申请人 |
KIM YOUNGGYUN;BHAKTA BHAVESH G.;GRUETTER DAVID R. |
发明人 |
KIM YOUNGGYUN;BHAKTA BHAVESH G.;GRUETTER DAVID R. |
| 分类号 |
G11B5/09;G11B20/14;H03L7/085;H03L7/087;(IPC1-7):G11B5/02;G11B19/02;G11B21/02 |
主分类号 |
G11B5/09 |
| 代理机构 |
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