发明名称 |
Process for producing an isolated planar high speed pin photodiode with improved capacitance |
摘要 |
A method is shown for producing a PIN photodiode having low parasitic capacitance and wherein an intrinsic layer of the photodiode can be made arbitrarily thin. A fabrication substrate is lightly doped to have a first conductivity type in order to form the intrinsic layer of the photodiode. A first active region of the photodiode having the first conductivity type is formed on a first surface of the fabrication substrate. An oxide layer is also formed upon the first surface of the fabrication substrate. A first glass layer is formed on a first surface of a handling substrate. The first surface of the handling substrate is bonded to the first surface of the fabrication substrate. A second surface of the fabrication substrate is then lapped to a obtain a preselected thickness of the intrinsic layer. A second active region of the photodiode having a second conductivity type is formed on the second surface of the fabrication substrate. A groove is etched from the second surface of the fabrication substrate through the intrinsic region to the first surface in order to isolate the photodiode. A second glass layer may be formed on a second surface of the handling substrate to further reduce parasitic capacitance.
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申请公布号 |
US6458619(B1) |
申请公布日期 |
2002.10.01 |
申请号 |
US20000505230 |
申请日期 |
2000.02.16 |
申请人 |
INTEGRATION ASSOCIATES, INC. |
发明人 |
IRISSOU PIERRE |
分类号 |
H01L31/0352;H01L31/105;(IPC1-7):H01L21/00 |
主分类号 |
H01L31/0352 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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