| 摘要 |
PROBLEM TO BE SOLVED: To reduce an influence of unevenness of scanning of a polygon mirror on image quality. SOLUTION: This clock generating circuit is provided with: a delay chain part 413 for generating a plurality of delayed clocks by bit-by-bit delaying a clock from a generator serving as a reference; a synchronization detecting part 414 for selecting a plurality of delayed clocks (synchronously delayed clocks) synchronized with an index signal serving as for a reference of an end part from the delay chain part and outputting the number of delay steps of the delay chain part as the synchronization information from the synchronously delayed clocks; a table 402 for holding the information of optical scanning unevenness; a synchronization switching part 415 for generating, from the synchronized delayed clocks, the synchronization information and the unevenness information, a selection signal to select a delayed clock of a particular phase from among a plurality of the synchronization information, and a signal selecting part 416 for selecting a delayed clock according to the selection signal from among a plurality of the delayed clocks. |
