SIGNAL GENERATING CIRCUIT, CLOCK RESTORING CIRCUIT, VERIFYING CIRCUIT, DATA SYNCHRONIZING CIRCUIT AND DATA RESTORING CIRCUIT

摘要

PROBLEM TO BE SOLVED: To solve several problems on design in the boundary of the maximum operating speed of a circuit element constituting a clock restoring circuit when a clock frequency is high. SOLUTION: A clock restoring circuit 30 capable of executing a series of repeating N cycles (N>=2) is provided with N piece of rising edge latches 40 which are respectively connected for receiving serial data streams to be triggered by each different rising edge of the series of repeating N cycles for fetching the rising edge samples of the data, N pieces of falling edge latches 42 which are respectively connected for receiving the data streams to be triggered by each different falling edge of the series of repeating N cycles for fetching the falling edge samples of the data, and sample processing means for processing those samples so that clock signals can be restored from the data streams.