| 摘要 |
PROBLEM TO BE SOLVED: To provide a DS3(digital signal level 3) demapping circuit that can reduces a delay in a data signal in the case of demapping from an STM 1(synchronous transfer mode 1) signal to a VC3(virtual container 3) signal. SOLUTION: Buffer memories 3, 5 for a data signal from the STM1 signal to the VC3 signal are placed in parallel for configuring a sole stage, and the write control of the buffer memories 3, 5 is made, on the basis of a result of an AU(administrative unit) pointer processing, and read control is conducted according to the result of staff information processing in the VC3.
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