| 摘要 |
The invention relates to a processor arrangement for security-related applications, comprising a memory (10) for storing memory contents in an encoded and compressed form, an arithmetic unit (12) and a device (14) for decoding (14a) and decompressing (14b) the encoded and compressed memory contents, the device for decoding and decompressing being arranged between the memory and the arithmetic unit in terms of data flow. The encoding time for security-related applications is reduced by compressing data before it is encoded. Furthermore, the required amount of memory is likewise reduced. Both chip surface and power consumption of the processor arrangement for security-related applications can be saved, this being especially advantageous for a chip card (26) comprising a processor arrangement for security-related applications. |
