DSP intercommunication network

摘要

A multi-processor system includes a global bus (14) with a global address space and a plurality of processor nodes (10). Each of the processor nodes (10) has a CPU (20) interfaced with a local bus having a local address space. A dual port SRAM (DPSRAM) (34) is provided for interfacing between the global bus (14) and the local bus (30). Each DPSRAM (34) for each processor core (10) has a defined address space within the global bus address space. Whenever any of the global resource writes to the particular processor node (10), it is only necessary to address the designated DPSRAM (34) and transfer data thereto. The act of transferring the data thereto will generate an interrupt to the associated CPU (20) which will then cause it to read the received data on the local bus by addressing its associated DPSRAM (34). This results in only a single access cycle for data transfer. Each of the CPU's (20) can communicate directly with another of the CPU's (20) through an interprocessor communication network. This network includes a Bi-FIFO (38). The CPU (20) is operable to interface with a predefined type of memory having a defined memory access protocol different from that of the Bi-FIFO (38). Therefore, a translator circuit is required to convert memory access commands and data flow to a compatible format with that of Bi-FIFO (38). This includes a programmable bi-directional pipeline circuit (600) and also a predecode circuit (618) to allow selection of one of a plurality of Bi-FIFOs to allow the CPU (20) to communicate with different Bi-FIFOs within the same memory space.