| 摘要 |
A delay lock loop circuit, in accordance with the present invention includes a delay lock loop unit having a power down mode. The delay lock loop unit includes a delay line having an input and an output. The input receives a first clock signal to generate a modified clock signal at the output. A phase detector is coupled to the input and the output of the delay line for comparing the first clock signal and the modified clock signal. A delay line control unit is coupled to the phase detector and the delay line for adjusting delay in the delay line in accordance with a control signal from the phase detector. A counter circuit is included for updating the delay lock loop unit to account for delay line drift during the power down mode by periodically generating an update signal which permits the delay lock loop unit to update in the power down mode.
|
