| 摘要 |
An apparatus and method that minimize the hardware and computation time needed to generate 64 bit addresses is described. To generate a 64 bit address, an address generation unit may need to add a 64 bit base value, a 64 bit index value, and a 32 bit displacement value to a 64 bit segment descriptor table address. The address generation unit can include a first adder and a second adder. The first adder can add a displacement to a first portion of the segment descriptor table address to generate an intermediate result. The intermediate result can be concatenated with a second portion of the segment descriptor table address and this concatenated result can be conveyed to the second adder. The second adder can add the concatenated result to a base value and an index value to generate a virtual address. To insure that the first adder does not generate a carry bit, the segment descriptor table address is required to be aligned on an address boundary and the displacement value is required not to exceed a maximum value. The address boundary can be an integer multiple of a fixed number of bytes and a fault can be generated if the segment descriptor table address is not aligned on this boundary.
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