| 摘要 |
PROBLEM TO BE SOLVED: To provide an evaluation/inspection system of a high speed bus capable of performing a test by the worst pattern in consideration of the maximum transfer load and crosstalk by a single device for the high speed bus in the device without requiring an external device. SOLUTION: An exclusive OR circuit 22 takes an exclusive OR of an initial value and an inversion bit select signal both from a table 21, output from a latch circuit 24. A check bit adding circuit 23 adds a check bit to data from the exclusive OR circuit 22, the latch circuit 24 latches data from the check bit adding circuit 23 and transfers it to a module B3 via the high speed bus 10. A check bit inspection circuit 31 of the module B3 performs error check based on the check bit of the transferred data and transmits its check result to a CPU 1 as error notification/detailed information. |
