发明名称 REDUNDANT MEMORY CIRCUIT FOR ANALOG SEMICONDUCTOR MEMORY
摘要 <p>PROBLEM TO BE SOLVED: To enhance the capability of redundancy replacement by reducing deterioration of a reproduced signal by redundancy replacement. SOLUTION: The redundant memory circuit for an analog semiconductor memory is provided with a cell array (ACLA) in which a plurality of sectors (SC) consisting respectively of a plurality of memory cells and redundant sector (RSC) for redundancy-replacing a defective sector are arranged, and a word line selecting means (WLDEC) arranged at a first end of the cell array and end of selecting a word line of the cell array, and in this circuit, the sectors are accessed successively in order from the first end to the second end or from the second end to the first end, while the redundant sector is accessed in the case of the order of access for defective sectors and an an analog value is written in a memory cell as it is. The redundant sectors are arranged respectively at the first end and the second end of the cell array, this defective sector is redundancy-replaced by a redundant sector being near to the defective sector.</p>
申请公布号 JP2002269994(A) 申请公布日期 2002.09.20
申请号 JP20010066277 申请日期 2001.03.09
申请人 OKI ELECTRIC IND CO LTD;OKI MICRO DESIGN CO LTD 发明人 SUGIO KENICHIRO
分类号 G06F12/16;G10L19/00;G11C7/16;G11C16/02;G11C16/06;G11C16/08;G11C16/30;G11C27/00;G11C29/00;G11C29/04;(IPC1-7):G11C29/00 主分类号 G06F12/16
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