| 摘要 |
<p>A PLL frequency synthesizer (1) is provided with a switch circuit (10) interposed between a low-pass filter circuit (103) and a voltage-controlled oscillator (104). The switch circuit (10) is controlled based on a control signal (Sent) to open/close control a feedback loop lying between the low-pass filter circuit (103) and the voltage-controlled oscillator (104). Namely, the switch circuit (10) is opened according to a path-opening instruction of a feedback loop based on the control signal (Scnt) to open the feedback loop, thereby stopping the operation of the feedback loop. If this stop operation is controlled according to the control signal (Sent) so as to be carried out during a period in which a pseudo correction pulse is outputted from a charge pump circuit (102) for each phase comparison cycle of a phase comparator (101), then spurious generation incident to the pseudo correction pulse can be suppressed. In this way even a spurious characteristic in a lock state can be improved while ensuring a high-speed lockup characteristic to thereby implement satisfactory communication quality. <IMAGE></p> |
