发明名称 SECONDARY MEMORY DEVICE FOR CONDUCTING SECURITY VIA USB INTERFACE BY USING PC BASED CRYPTO CHIP AND FLASH MEMORY
摘要 PURPOSE: A security memory device is provided to embed a crypto chip having an encryption algorithm and encrypt/store data by using a USB(Universal Serial Bus) port so that it can prevent the data, stored at a PC, from illegally being used. CONSTITUTION: The device comprises a USB controller, and a crypto chip. The USB controller includes a USB core and an MCU(Memory Control Unit). The USB core receives external serial data via a USB port, buffers the data and performs a serial I/O operation on the data. The MCU receives data by 8 bits from the USB core. In a case that the data is an instruction of a module data request, the MCU reads module data from a PROM of the crypto chip and outputs the module data to an input end of the USB core. In a case that the data is an instruction of a crypto chip control, the MCU outputs 17 bit data, including 16 bits received afterwards, to an input end of a buffer of the crypto chip or outputs the 16 bits to an input end of the USB core. The crypto chip includes a buffer, a KSE96 block, a controller, a mode checker, a scrambler, and an RSA operator. The buffer receives the data from the MCU, and transmits the data to one among the KSE96 block, the controller, the mode checker, and the RSA operator, or receives data from the scrambler and transmits the data to the MCU. The KSE96 block receives the data from the buffer, encrypts the data based on a private key encryption algorithm and transmits the encrypted data to the scrambler. The controller receives a code word, controls the crypto chip to encrypt or decrypt the data if the code word is a data process instruction, and controls the crypto chip to conduct a key generation and process if the code word is a key process instruction. The mode checker receives 4 byte input value and 4 byte reference value from the buffer, compares them with values of DBG_Table, and transmits a comparison result, a false or a true, to the controller. The scrambler receives 96 bit data and an initial value of the 96 bit data from the KSE96 block, performs a feedback XOR operation on the received data, and transmits the operation result to the buffer. The RSA operator receives an external control signal and input data, and outputs an authentication key or decrypted data by using an RSA encryption algorithm.
申请公布号 KR20020071274(A) 申请公布日期 2002.09.12
申请号 KR20010011319 申请日期 2001.03.06
申请人 HAN, SEUNG JO 发明人 HAN, SEUNG JO
分类号 G06F12/14;(IPC1-7):G06F12/14 主分类号 G06F12/14
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