发明名称 COMPLEMENTARY ACCUMULATION-MODE JFET INTEGRATED CIRCUIT TOPOLOGY USING WIDE (> 2eV) BANDGAP SEMICONDUCTORS
摘要 <p>A method and device produced for design, construction, and use of integrated circuits in wide bandgap semiconductors, including methods for fabrication of n-channel and p-channel junction field effect transistors (40, 50) on a single wafer or die, such that the produced devices may have pinchoff voltages of either positive or negative polarities. A first layer of either p-type or n-type is formed as a base. An alternating, channel layer of either n-type or p-type is then formed, followed by another layer of the same type as the first layer (79). Etching is used to provide contacts for the gates, source, and drain of the device. In one variation, pinchoff voltage is controlled via dopant level and thickness and channel region. In another variation, pinchoff voltage is controlled by variation of dopant level across the channel layer; and in another variation, pinchoff voltage is controlled by both thickness and variation of dopant level.</p>
申请公布号 WO2002071449(A2) 申请公布日期 2002.09.12
申请号 US2002006431 申请日期 2002.03.04
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