发明名称 HIGH SPEED NETWORK PROCESSOR
摘要 A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.
申请公布号 WO02071206(A2) 申请公布日期 2002.09.12
申请号 WO2002EP01955 申请日期 2002.01.31
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION;COMPAGNIE IBM FRANCE 发明人 CALVIGNAC, JEAN, LOUIS;GOETZINGER, WILLIAM, JOHN;HANDLOGTEN, GLEN, HOWARD;HEDDES, MARCO, C.;LOGAN, JOSEPH, FRANKLIN;MIKOS, JAMES, FRANCIS;NORGAARD, DAVID, ALAN;VERPLANKEN, FABRICE
分类号 H04L12/56 主分类号 H04L12/56
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