发明名称 |
Frame rate controller |
摘要 |
A frame rate controller 20 is provided for controlling the frame refresh rate of an active matrix display. The controller 20 comprises a first circuit such as a preloadable synchronous counter 21 which counts vertical synchronization signals VSYNC and supplies an enable signal FE for every Nth frame of data, where N is an integer greater than zero and is selectable. A gating arrangement 26 is controlled by the enable signal FE so that an active matrix display is refreshed for every Nth frame of data, thus allowing a reduction in power consumption of the display.
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申请公布号 |
US2002126083(A1) |
申请公布日期 |
2002.09.12 |
申请号 |
US20020092372 |
申请日期 |
2002.03.05 |
申请人 |
CAIRNS GRAHAM ANDREW;BROWNLOW MICHAEL JAMES |
发明人 |
CAIRNS GRAHAM ANDREW;BROWNLOW MICHAEL JAMES |
分类号 |
G02F1/133;G09G3/20;G09G3/36;G09G5/00;G09G5/18;(IPC1-7):G09G3/36 |
主分类号 |
G02F1/133 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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