Video apparatus, notably video decoder, and process for memory control in such an apparatus

摘要

The invention concerns a video apparatus with a digital decoder (6) using a first memory (8) and with an On-Screen Display (OSD) circuit (12) using a second memory (10), wherein the digital decoder (6) and the second memory (10) are linked via a bus in order to realise DMA transfers between the first memory (8) and the second memory (10). A process for controlling a video apparatus with a digital decoder (6) using a first memory (8) and with an OSD circuit (12) using a second memory (10) is proposed to have the following steps: issuing a request for the OSD circuit (12) to use more than a given size in the second memory (10), realising a DMA transfer from the second memory (10) to the first memory (8).