发明名称 METHOD FOR FORMING FINE PATTERN, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To form a fine pattern having both of a groove pattern and a hole pattern in the process of manufacturing a semiconductor device without carrying out vacuum vapor deposition. SOLUTION: A three-layer resist having a silylation resist 14 as the intermediate layer is formed by coating ((a), (b)). After the upper layer resist pattern 16 is formed ((c), (d)), the resist is exposed to a gas 17 containing Si element (e) to silylate the intermediate layer to form a Si-containing region 18 (f). Then a hole pattern 20 is formed in the upper layer resist pattern 16 (g), and the intermediate layer and the lower layer resist are etched to form a hole pattern 21 (h). After the upper layer resist pattern 16 is removed (i), the part not silylated is subjected to dry etching to form a groove pattern 22 (j).
申请公布号 JP2002258492(A) 申请公布日期 2002.09.11
申请号 JP20010059798 申请日期 2001.03.05
申请人 SEMICONDUCTOR LEADING EDGE TECHNOLOGIES INC 发明人 SATO ISAO
分类号 G03F7/11;G03F7/26;G03F7/38;G03F7/40;H01L21/027 主分类号 G03F7/11
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