| 摘要 |
PURPOSE: A synchronous static RAM is provided to read data in a reading cycle itself and to supply a write pass-through for a high speed in the case that data written previously right now are read. CONSTITUTION: A pass gate(40) which passes an output of a data input buffer(20) to a Mux output node is inserted into a basic circuit of a static RAM comprising a click buffer(10), a data input buffer(20), and an output buffer(30). The pass gate(40) is controlled by a pass gate control unit(50). In the case that a signal(web) output through a record enable buffer is low, the pass gate control unit(50) makes a fixed pulse width and turns-on the pass gate(40), passes data(wdwpt) being inputted through a data input buffer to an output terminal of the Mux output node, latches the data(wdwpt), and turns-off the pass gate(40) at the end of a pulse width. The pass gate control unit(50) comprises the first inverter(51) which inverts an output signal of a write enable buffer, a delay unit(52) which delays an output signal of the first inverter(51), the second inverter(53) which inverts an output signal of the delay unit(52), a NOR gate(54) which receives an output signal of the second inverter(53) and an output signal of the write enable buffer, and the third inverter(55) which inverts an output signal of the NOR gate(54).
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