| 摘要 |
PROBLEM TO BE SOLVED: To provide a display device having excellent display quality and a large margin in timing. SOLUTION: The signal line driving circuit in the display device has a shift register 1. Each register circuit 2 in the shift register 1 has two stages of latch circuits 3, 4 which are cascaded and an inverter 5 which is connected to the output terminals of the latch circuit 14 of the poststage and clocked inverters 5, 6 which are connected to the output terminals of the inverter 5. Since the number of gate stages from a time when a start signal is inputted to the shift register 1 till a time when control signals are inputted to analog switches supplying an analog signal to signal lines is minimized in the driving circuit, the driving circuit becomes to be hardly affected by variation of characteristics of TFTs(thin film transistors) constituting the circuit and the operating margin is broadened. Moreover, since timing when analog switches are turned from OFF to ON are shifted in a pulse cutting circuit, anxiety that adjacent analog switches are turned ON simultaneously is eliminated in the driving circuit.
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