发明名称 Signal-processing circuit, and recording and playback apparatus employing the same
摘要 A signal-processing circuit in which two-stage equalization is carried out by using first and second equalization circuits provided on the upstream and downstream sides from a phase locked loop circuit, respectively, is provided, wherein the first equalization circuit on the upstream side from the phase locked loop circuit is composed of a transversal filter, to minimize an equalization error caused by the first equalization circuit, thereby stabilizing the operation of the phase locked loop circuit. Another signal-processing circuit including an analog-to-digital converter and a digital phase locked loop circuit for receiving the output from the analog-to-digital converter, and a recording and playback apparatus using the same are also provided, wherein the output from the analog-to-digital converter is input as the digital signal in the digital phase locked loop circuit, to fetch a detection point voltage, thereby stabilizing the operation of the phase locked loop circuit without the need of provision of any analog circuit.
申请公布号 US2002122478(A1) 申请公布日期 2002.09.05
申请号 US20010992606 申请日期 2001.11.14
申请人 HIRASAKA HISATO 发明人 HIRASAKA HISATO
分类号 G11B20/10;H04B3/06;H04L25/03;(IPC1-7):H03H7/30;H03H7/40 主分类号 G11B20/10
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