| 摘要 |
There is provided an IC testing apparatus capable of testing ICs each having a memory portion and a logic portion formed together on one chip within a time duration shorter than that in the case that the ICs are tested using two IC testing apparatus. There are provided, in an IC tester 10 having a predetermined number of channels CH1 through CH512 for supplying driving signals to ICs under test, IC sockets SK1 through SK8 the number of which is the same as the number of memory portions that can be tested simultaneously by the IC tester, the number of the IC sockets being determined by the number of channels of the IC tester and the number of channels required for testing a memory portion of an IC under test, and further, a switching circuit 21 is provided between those IC sockets and the channels of the IC tester. This switching circuit 21 switches between a state in which driving signals for testing the memory portions of ICs are supplied to all of the IC sockets and a state in which driving signals for testing logic portions of ICs under test are supplied to a part of the IC sockets, and a testing is performed.
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