发明名称 Efficient store machine in cache based microprocessor
摘要 A method of retiring operations to a cache. Initially, a first operation is queued in a stack such as the store queue of a retire unit. The first operation is then copied, in a first transfer, to a latch referred to as the miss latch in response to a resource conflict that prevents the first operation from accessing the cache. The first operation is maintained in the stack for the duration of the resource conflict. When the resource conflict is resolved, the cache is accessed, in a first cache access, with the first operation from the stack. Preferably, the first operation is removed from the stack when the resource conflict is resolved and the first cache access is initiated. In the preferred embodiment, the first operation is maintained in the miss latch until the first cache access results in a cache hit. One embodiment of the invention further includes accessing the cache, in a first miss access, with the first operation from the miss latch in response to a cache miss that resulted from the first cache access. In a presently preferred embodiment, a second access is executed to access the cache with a second operation queued in the stack in response to a cache hit resulting from the first cache access. The first and second cache accesses preferably occur in consecutive cycles. Typically, the first and second operations are store operations that are queued in the stack in program order. In one embodiment the first operation is removed from the stack upon resolving of the resource conflict.
申请公布号 US6446170(B1) 申请公布日期 2002.09.03
申请号 US19990232239 申请日期 1999.01.19
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 CHAN KIN SHING;HICKS DWAIN ALAN;MAYFIELD MICHAEL JOHN;TUNG SHIH-HSIUNG STEPHEN
分类号 G06F9/38;(IPC1-7):G06F12/00 主分类号 G06F9/38
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