| 摘要 |
A serial interface circuit capable of converting a large volume of data into packets based on a predetermined standard for transmission and reception and capable of performing smooth transmission and reception processing, configured so that, in a reception operation, a request packet generation circuit generates a request packet and calculates the maximum length of data of the response packet with respect to the request packet transmitted and a transaction controller compares the maximum length of data maxpl with the remaining memory amount of the response use FIFO and, when the remaining memory amount is larger than the maximum length of data, transmits the request packet. When the remaining memory amount is smaller than the maximum length of data maxpl, the output of the request packet to the link core, that is, the transmission of the request packet to the other node, is temporarily suspended until the remaining memory amount becomes larger than the maximum length of data maxpl.
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