发明名称 BIT ERROR INSERTION CIRCUIT FOR PN PATTERN GENERATOR
摘要 PROBLEM TO BE SOLVED: To provide a bit error insertion circuit for a PN pattern generator that can set a bit error to an optional position of a bit stream configuring a PN pattern signal. SOLUTION: The bit error insertion circuit for a PN pattern generator comprises a PN pattern generating section 1 that generates a PN pattern signal, an error insertion timing generating section 12 that generates an insertion timing of a bit error to be inserted to the PN pattern signal, an error generating section 13 that generates a bit error insertion signal to be inserted to the PN pattern signal, an error inserting position decision section 14 that decides a bit location of the bit error inserted to the PN pattern signal, and a PN pattern/PN error insertion section 3 that inserts the PN pattern signal to input data and inserts a 1-bit error to an optional position of the bit stream configuring the PN pattern signal.
申请公布号 JP2002247143(A) 申请公布日期 2002.08.30
申请号 JP20010046000 申请日期 2001.02.22
申请人 TOYO COMMUN EQUIP CO LTD 发明人 SAITO GEN
分类号 H03K3/78;H04L29/14;(IPC1-7):H04L29/14 主分类号 H03K3/78
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