LAYOUT STRUCTURE FOR BIT LINE BOOSTING CAPACITOR OF SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE: A layout structure for bit line boosting capacitor of semiconductor memory device is provided to improve the coupling efficiency of a bit line boosting capacitor by including a first insulation transistor, a second insulation transistor, and an MOS(Metal Oxide Semiconductor) transistor in a semiconductor memory device. CONSTITUTION: A memory cell array(100L,100R) includes a first bit line, a second bit line, and a plurality of memory cells connected with the first and the second bit line. A sensing amplification circuit(120) senses an electric potential difference between the first and the second bit line. A first insulation transistor which includes a source region, a drain region and a gate connects/insulates the first bit line with/from the sensing amplification circuit(120). A second insulation transistor which includes a source region, a drain region and a gate connects/insulates the second bit line with/from the sensing amplification circuit(120). An MOS transistor has a source region in common with the first and the second insulation transistor, and includes an uneven-shaped gate.