发明名称 |
Cache memory system |
摘要 |
<p>A cache memory system (1) having a small-capacity and high-speed access cache memory (6) provided between a processor (CPUi) and a main memory (CSM), including a software cache controller (8) for performing software control for controlling data transfer to the cache memory (6) in accordance with a preliminarily programmed software and a hardware cache controller (9) for performing hardware control for controlling data transfer to the cache memory (6) by using a predetermined hardware such that the processor (CPUi) causes the software cache controller (8) to perform the software control but causes the hardware cache controller (9) to perform the hardware control when it becomes impossible to perform the software control. <IMAGE></p> |
申请公布号 |
EP1235154(A2) |
申请公布日期 |
2002.08.28 |
申请号 |
EP20020003446 |
申请日期 |
2002.02.14 |
申请人 |
SEMICONDUCTOR TECHNOLOGY ACADEMIC |
发明人 |
SAKAI, ATSUSHI;AMANO, HIDEHARU |
分类号 |
G06F9/45;G06F9/52;G06F9/54;G06F12/08;(IPC1-7):G06F12/08 |
主分类号 |
G06F9/45 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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