发明名称 Method and apparatus for improving auto-placement in semiconductor integrated circuit design
摘要 After auto-placement, nets are classified into groups each having logically equivalent signals, terminal placement range of each net is determined, and overlap regions of respective pairs of the ranges in the same group is obtained. In each net of each pair having this overlap region, such an input terminal in the overlap region is found out that an wiring length between an output terminal and the input terminal is maximum (S30 and S31), and a decrement DELTA in wiring length is calculated assuming that the two input terminals found out are exchanged (S32). If DELTA>0 (S33), then the two input terminals are exchanged with each other (S34). Such processing is repeated until DELTA<=0.
申请公布号 US6442744(B1) 申请公布日期 2002.08.27
申请号 US19990457734 申请日期 1999.12.10
申请人 FUJITSU LIMITED 发明人 ISHII HIDEAKI
分类号 H01L21/82;G06F17/50;(IPC1-7):G06F17/50 主分类号 H01L21/82
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