Interactive method of optimum LSI layout including considering LSI chip size, test element groups, and alignment marks

摘要

A method of designing an LSI layout at a stage of making an LSI layout plan for each of a plurality of LSI chips before entering into the design of masks, which includes judging whether or not all the LSI chips can be arranged on a single wafer along with other (nonelectronic) components, based on a given LSI chip size and referring to the information on the other components. An LSI an LSI chip yield per water and/or a manufacturing cost per LSI chip are calculated, whereby an LSI layout designer can quickly and easily, within a limited LSI development term, determine how much the LSI chip size can be downsized for economical production of the LSI chip, referring to the results of the above judgment and calculation.