| 摘要 |
An improved MOS IC is disclosed having a low standby current ESD voltage clamp for the power and ground pads. The ESD voltage clamp uses the vertical PNP transistors inherently available in CMOS device fabrication by using the P+ source drain regions as the emitter, the N+ source drains as base contacts, the N wells as bases, and the P substrate as collectors. Thus the advantages of rapid voltage spike protection may be obtained with no increase in the number of masking steps or device fabrication complexity. The vertical PNP bipolar transistors are arranged in a Darlington configuration with the last transistor in the chain having a base region connected to both a resistor charging network connected to the power supply, and a capacitive network connected to the ground potential. A PMOS transistor is attached across the emitter and base of the last bipolar transistor in the Darlington chain to reduce the voltage overshoot and regulate the charge on the capacitor network.
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