发明名称 Multiphase clock generator
摘要 The Sync State outputs are used in combination with the multiple phase outputs to generate and error signal which is operable to generate a control voltage which controls the frequency of the MVCO and to-generate a shifted clock which is divided in a sequential circuit to generate the quadrature clock with a frequency F.
申请公布号 US6441667(B1) 申请公布日期 2002.08.27
申请号 US20010820460 申请日期 2001.03.29
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 BOERSTLER DAVID WILLIAM;MONTOYE ROBERT KEVEN;NOWKA KEVIN JOHN
分类号 G06F1/04;H03L7/087;H03L7/091;H03L7/099;(IPC1-7):G06F1/04 主分类号 G06F1/04
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