| 摘要 |
A semiconductor memory device having serial access read mode including a latency period and a serial access period is provided. Semiconductor memory device (100) can include sense amplifier (110), a reference voltage generator (200), and a period detection circuit (101). Period detection circuit (101) can provide a control signal (RCL) indicating the latency period or the serial access period. Reference voltage generator (200) can provide a reference voltage (REF) having a first potential during the latency period and a second potential during the serial access period. In this manner, it may be possible to increase the speed of reading memory cell data by reducing the timing differences between reading a memory cell having a first data state and a memory cell having a second data state.
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