| 摘要 |
PROBLEM TO BE SOLVED: To provide an SRAM which can increase the integration degree of a memory cell array. SOLUTION: Memory cells(MCs) 210 have five conductive layers in the upper part of a field. A flip-flop is constituted of two gate-to-gate electrode layers situated in the first-layer conductive layer, a drain-to-drain connection layer situated in the second-layer conductive layer and a drain-to-gate connection layer situated in the third-layer conductive layer. Bit lines 61a, the inverse of bit lines 61b and VDD interconnections 33 (power supply lines) of the memory cells(MCs) 210 are extended in the Y-direction, and VSS interconnections 55 (ground lines) are extended in the X-direction. First pairs 240 and second pairs 250 are situated in pairs of the bit lines 61a, and the inverse of the bit lines 61b, and they are connected to the power supplies VDDs via power-supply separation circuits 230, in each of the first pairs 240 and the second pairs 250 as one set. In the first pairs 240 and the second pairs 250 as one set, the memory cells(MCs) 210 in the first pairs 240 and the memory cells(MCs) 210 in the second pairs 250 use the VDD interconnections 33 in common. |
