发明名称 QUADRATURE FREQUENCY DIVISION MULTIPLEX SIGNAL RECEIVER
摘要 <p>PROBLEM TO BE SOLVED: To easily obtain an exact synchronization signal on the receiving side in the case of receiving an OFDM signal. SOLUTION: An exact clock signal to drive a receiver is generated by providing an IFFT circuit to generate a multilevel QAM modulation signal, a guard interval setting circuit and a clock signal generating circuit to drive both of the circuits, setting phases as prescribed values at starting points of a plurality of symbol sections by the IFFT circuit, generating a pilot signal of high-order frequency with prescribed frequency ratio with the clock signal, making the pilot signal be continuously transmitted over a plurality of symbol sections including guard interval sections on the transmitter side of the OFDM signal, and obtaining the pilot signal by demodulating it on the receiver side.</p>
申请公布号 JP2002237798(A) 申请公布日期 2002.08.23
申请号 JP20020016841 申请日期 2002.01.25
申请人 VICTOR CO OF JAPAN LTD 发明人 TAKAHASHI NOBUAKI;TAKAHASHI SUSUMU;SUGIYAMA KENJI
分类号 H04J11/00;H04L7/00;(IPC1-7):H04J11/00 主分类号 H04J11/00
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