发明名称 SEMICONDUCTOR MEMORY
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor memory in which suppression of deterioration of endurance and sufficient compensation of deterioration of imprint can be performed simultaneously. SOLUTION: Call plate driver circuits 11, 12 perform output for drive lines 9, 10 for applying voltage to ferroelectric memory cells 3, 4 when data is read by control of a control circuit 16. The cell plate drive circuits 11, 12 are connected to an amplifier circuit control signal line 18 controlling an amplifier circuit 17 through the control circuit 16, and switch a potential of voltage outputted to the drive lines 9, 10 before and after of amplifying operation for potentials of bit lines 8, 9 of the amplifier circuit 17.
申请公布号 JP2002237181(A) 申请公布日期 2002.08.23
申请号 JP20010032780 申请日期 2001.02.08
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 IWANARI SHUNICHI
分类号 G11C11/22 主分类号 G11C11/22
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