TIMING EXTRACTING CIRCUIT OF OPTICAL RECEIVER USING FREQUENCY CLOCK THAT IS HALF THE DATA TRANSMISSION RATE, AND DUTY SHIFT ADAPTIVE CIRCUIT OF OPTICAL TRANSCEIVER

摘要

An improved timing extracting circuit of optical receiver, particularly using a frequency clock that is half the data transmission rate, and a duty shift adaptive circuit of optical transceiver. The timing extracting circuit has a detector circuit that, using a PLL circuit including a phase comparator circuit for performing a phase comparison between a data signal of a bit rate B (bit/s) and a clock signal of B/2 (Hz) at an interval of 2/B (sec), detects, in response to reception of a data signal of a predetermined pattern, that the phase comparator circuit no longer outputs any phase comparison information; and further has a control circuit responsive to that detection to control the phase of the clock signal so as to maintain the synchronization. The duty shift adaptive circuit controls, based on the result of determination of the duty between the input data before the synchronization of the PLL circuit is established and the input data after the establishment, the data identification phase before and after the establishment.