发明名称 Methods of fabricating high-reliability and high-efficiency trench isolation for semiconductor devices
摘要 The trench-isolation structures for fabricating semiconductor devices using two different multilayer masking structures are disclosed by the present invention, in which the extended buffer spacers located in the isolation regions are formed on the sidewalls of two different multilayer masking structures having a masking dielectric layer on a pad-oxide layer and a masking dielectric layer on a conductive layer over a gate-oxide layer. The extended buffer spacers not only act as the etching mask for forming the trenches in the semiconductor substrate but also play significant roles for obtaining high-reliability and high-efficiency trench isolation of the present invention. The first role of the extended buffer spacers of the present invention is to offer the buffer regions for preventing the bird's beak formation around the edge of the active region during the thermal oxidation of the trench surface, so that the active area used to fabricate the active device is not sacrificed. The second role of the extended buffer spacers of the present invention is to create the buffer regions in the semiconductor substrate for the field-encroachment implant, so that much better efficiency of trench isolation can be obtained without reducing the active area. The third role of the extended buffer spacers of the present invention is to offer the capping-dielectric layers near the edges of the trench corners for eliminating the leakage due to the sharp trench corners. Therefore, the present invention may offer high-reliability and high-efficiency isolation for advance high-density integrated-circuit fabrication with maximized active area and minimized isolation area.
申请公布号 US2002115270(A1) 申请公布日期 2002.08.22
申请号 US20010789568 申请日期 2001.02.22
申请人 WU CHING-YUAN 发明人 WU CHING-YUAN
分类号 H01L21/762;(IPC1-7):H01L21/36 主分类号 H01L21/762
代理机构 代理人
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