Line layout method for wiring plane for integrated semiconductor device positions lines in wiring plane in order of their circuit activity

摘要

The line layout method determines the circuit activity for each line and positions the lines on the wiring plane beginning with the line exhibiting the greatest circuit activity for the highest wiring plane, followed by each of the remaining lines in order of decreasing circuit activity, or beginning with the line with the lowest circuit activity for the lowest wiring plane, followed by the remaining lines in order of increasing circuit activity. An independent claim for a line layout device for a wiring plane for an integrated semiconductor device is also included.