| 摘要 |
A status phase processor for a data pattern recognizer or correlator provides an optimized synchronization signal. The synchronization signal can be utilized to adjust the data sampling clock. The data pattern correlator utilizes two or more samples per symbol of the signal which is expected to be received. The system provides high accuracy correlation without significant hardware and software overhead. The status phase processor relies on a counter circuit and a logic circuit for generating the synchronization signal.
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