发明名称 |
Delay locked loop incorporating a ring type delay and counting elements |
摘要 |
Disclosed is a delay locked loop for use in a semiconductor memory device, for operating in low clock frequency applications that require a small chip size. The delay locked loop includes an input unit for receiving an external clock signal from which a clock input signal is created; a delay monitor for receiving a clock output signal to monitor a time delay introduced on the clock input signal; and a phase detection unit for receiving the clock input signal and an output of the delay monitor for determining a difference in phase between the clock input and output signals to produce a shift control signal. A shift register for controlling the adjustment of the time delay and a delay line for adjusting the time delay are also provided in the delay locked loop. Both the shift register and the delay line have a ring configuration on their outputs. The delay locked loop provided also includes a first and a second counter for counting the number of data signals outputted from the delay line and the shift register, respectively; a comparator for comparing these counted numbers; and an output unit for receiving the output of the delay line and the compared value to produce the clock output signal.
|
申请公布号 |
US6437618(B2) |
申请公布日期 |
2002.08.20 |
申请号 |
US20010888905 |
申请日期 |
2001.06.25 |
申请人 |
HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. |
发明人 |
LEE SEONG-HOON |
分类号 |
G11C11/407;H03K3/354;H03L7/081;(IPC1-7):H03L7/06 |
主分类号 |
G11C11/407 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|