发明名称 |
Multi-level cache controller |
摘要 |
A method and apparatus for accessing a cache memory of a computer graphics system, the apparatus including a frame buffer memory having a graphics memory for storing pixel data for ultimate supply to a video display device, a read cache memory for storing data received from the graphics memory, and a write cache memory for storing data received externally of the frame buffer and data that is to be written into the graphics memory. Also included is a frame buffer controller for controlling access to the graphics memory and read and write cache memories. The frame buffer controller includes a cache first in, first out (FIFO) memory pipeline for temporarily storing pixel data prior to supply thereof to the cache memories.
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申请公布号 |
US6437789(B1) |
申请公布日期 |
2002.08.20 |
申请号 |
US19990253474 |
申请日期 |
1999.02.19 |
申请人 |
EVANS & SUTHERLAND COMPUTER CORPORATION |
发明人 |
TIDWELL REED;PIMENTEL GARY |
分类号 |
G06F12/08;G09G5/393;(IPC1-7):G09G5/36 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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