| 发明名称 |
System and method for data pacing |
| 摘要 |
The present invention increases data transfer rate and reduces interrupt latency while avoiding a concomitant increase in interrupts to the host, by pacing the data flow between the UART and DSP using burst modes and wait modes.
|
| 申请公布号 |
US6438628(B1) |
申请公布日期 |
2002.08.20 |
| 申请号 |
US19990322952 |
申请日期 |
1999.05.28 |
| 申请人 |
3COM CORPORATION |
发明人 |
MESSERLY SHAYNE;KILLIAN HARRISON;ARNESEN DAVID |
| 分类号 |
G06F13/38;(IPC1-7):G06F13/00 |
主分类号 |
G06F13/38 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
|
| 地址 |
|
