SYNCHRONOUS SEMICONDUCTOR MEMORY

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which the data output timing can be set appropriately in accordance with the operation condition of word constitution or the like. SOLUTION: A DLL circuit 100 generates a control clock DLLCLK specifying the operation timing of a data output buffer 50 based on an external clock EXTCLK. The DLL circuit 100 comprises a dummy delay time adjusting section 130 and a phase control section 140. The phase control section 140 controls the delay time of the delay circuit 100 so that a feedback clock FBCLK and an external clock EXTCLK have the same phase. The dummy delay time adjusting section 130 adjusts the delay time of the feedback clock FBCLK for the control clock DLLCLK in accordance with operation conditions being variation factors of the processing time of the data output buffer 50.